The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Mar. 14, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Karim M Megawer, San Diego, CA (US);

Jongmin Park, San Diego, CA (US);

Thomas Mayer, Linz, AT;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/083 (2006.01); H03L 7/081 (2006.01); H03L 7/195 (2006.01);
U.S. Cl.
CPC ...
H03L 7/083 (2013.01); H03L 7/0818 (2013.01); H03L 7/195 (2013.01);
Abstract

This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.


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