The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Nov. 18, 2022
Applicant:

Halo Microelectronics International, Campbell, CA (US);

Inventors:

Rui Liu, Fremont, CA (US);

Sofjan Goenawan, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/08 (2006.01); H02M 3/06 (2006.01); H02M 3/156 (2006.01); H02M 3/157 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H02M 1/083 (2013.01); H02M 3/06 (2013.01); H02M 3/156 (2013.01); H02M 3/157 (2013.01);
Abstract

An apparatus includes a PWM ramp generator coupled between a switching node of a power converter and a first input of a comparator, the PWM ramp generator including a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node, and a PFM control circuit including an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.


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