The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2024
Filed:
Jan. 27, 2023
Texas Instruments Incorporated, Dallas, TX (US);
Venkateswar Kowkutla, Allen, TX (US);
Kazunobu Shin, Plano, TX (US);
Venkateswara Pothireddy, Mckinney, TX (US);
Siva Kothamasu, Frisco, TX (US);
John Apostol, Richardson, TX (US);
Raghavendra Santhanagopal, Mckinney, TX (US);
Rajagopal Kollengode Ananthanarayanan, Plano, TX (US);
Rejitha Nair, Southlake, TX (US);
Charles Gerlach, Dallas, TX (US);
Ravi Teja Reddy, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.