The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Mar. 18, 2022
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Bassam Abdel-Dayem, Santa Clara, CA (US);

Thomas A. Volpe, Austin, TX (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/5386 (2013.01); H01L 23/642 (2013.01); H01L 25/50 (2013.01);
Abstract

A semiconductor package can include a capacitance die. The package can have multiple dice (e.g., logic die, memory die) mounted on a substrate. Each die can include a power domain. The dice can be distributed on the substrate such that an extra space is present on the substrate between at least some of the dice. For example, an extra space may be present between two dice, at a corner of the substrate, or other locations. The extra space can disrupt a coplanarity of the semiconductor package. The capacitance die can be located in the extra space so as to establish the coplanarity with the other dice. The capacitance die can include a capacitor array electrically coupled to multiple power domains of the plurality of dice.


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