The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Aug. 06, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventor:

Khokan Chandra Paul, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/455 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02274 (2013.01); C23C 16/45536 (2013.01); H01J 37/32266 (2013.01);
Abstract

Examples of the present technology include semiconductor processing methods that may include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma may be generated at a delivered power within a first period of time when plasma power is delivered from a power source operating at a first duty cycle. The methods may further include transitioning the power source from the first duty cycle to a second duty cycle after the first period of time. A layer may be deposited on a substrate in the processing region of the semiconductor processing chamber from the generated plasma. The layer, as deposited, may be characterized by a thickness of 50 Å or less. Exemplary deposition precursors may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer.


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