The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Nov. 16, 2022
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Li Rosenbaum, Rishon Lezion, IL;

Elad Harush, Raanana, IL;

Omri Flint, Ramat Hasharon, IL;

Assignee:

APPLE INC., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0689 (2013.01); G06F 2212/7207 (2013.01);
Abstract

A System on Chip (SoC) includes a processor, a parity generation circuit, and a dispatcher circuit. The processor is configured to produce store instructions for storing data blocks in a Non-Volatile-Memory (NVM). The parity generation circuit is configured to calculate parity blocks over the data blocks in accordance with a redundant storage scheme, to send the parity blocks to the NVM, and to produce completion notifications with respect to the parity blocks. The dispatcher circuit is configured to dispatch the store instructions to the NVM. The processor is further configured to send one or more parity-barrier instructions that specify synchronization barriers over the store instructions and the parity, and the dispatcher circuit is configured to dispatch the store instructions to the NVM in compliance with the parity-barrier instructions and the completion notifications.


Find Patent Forward Citations

Loading…