Hash function with perfect hash component

Abstract

A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max<K, to ensure that input operands which differ only by H_select<=H_max bits, map to distinct hash values with no collisions.