The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Aug. 07, 2023
Applicant:

Next Silicon Ltd, Givatayim, IL;

Inventors:

Dan Shechter, Tel Aviv, IL;

Elad Raz, Ramat Gan, IL;

Assignee:

Next Silicon Ltd, Givatayim, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 12/0895 (2013.01); G06F 2212/1021 (2013.01);
Abstract

A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.


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