The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2024
Filed:
Feb. 28, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Prasanth Viswanathan Pillai, Bangalore, IN;
Swathi Gangasani, Bangalore, IN;
Vaskar Sarkar, Bangalore, IN;
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3167 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/3167 (2013.01); G01R 31/318508 (2013.01); G01R 31/318533 (2013.01); G01R 31/318536 (2013.01);
Abstract
An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.
Pillai, Prasanth. (2024). Methods and apparatus to implement a boundary scan for shared analog and digital pins (U.S. Patent No. 12130329). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12130329
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile