The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Mar. 24, 2023
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

William Mahany, West Islip, NY (US);

Ian Saturley, Warwickshire, GB;

Lakshmi Narasimhan, Chennai, IN;

Riyas Kattukandan, Kerala, IN;

Ramya Kuppusamy, Karnataka, IN;

Robert Zakowicz, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 69/22 (2022.01); G06F 9/4401 (2018.01); H04J 3/06 (2006.01); H04L 12/10 (2006.01);
U.S. Cl.
CPC ...
H04L 69/22 (2013.01); G06F 9/4418 (2013.01); H04J 3/0658 (2013.01); H04L 12/10 (2013.01);
Abstract

An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.


Find Patent Forward Citations

Loading…