The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Mar. 08, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghun Lee, Suwon-si, KR;

Kyoungjun Kim, Yongin-si, KR;

Sun Kim, Hwaseong-si, KR;

Seolyoung Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/56 (2010.01); H01L 25/13 (2006.01); H01L 33/06 (2010.01); H01L 33/32 (2010.01); H01L 33/44 (2010.01); H01L 33/48 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 33/56 (2013.01); H01L 25/13 (2013.01); H01L 33/06 (2013.01); H01L 33/32 (2013.01); H01L 33/44 (2013.01); H01L 33/486 (2013.01); H01L 33/62 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/005 (2013.01);
Abstract

A semiconductor light emitting device package includes a circuit board with an upper pad, a light emitting diode chip on the circuit board and having a first surface facing the circuit board and a second surface opposing the first surface, and the light emitting diode chip including a substrate, a semiconductor stack structure on the substrate that emits ultraviolet light, and electrodes connected to the semiconductor stack structure, connection bumps between the circuit board and the light emitting diode chip, the connection bumps connecting the upper pad and the electrodes, an underfill resin on the upper pad of the circuit board and covering at least a portion of a side surface of the light emitting diode chip, and a passivation layer on the light emitting diode chip and the underfill resin, the passivation layer covering the underfill resin and being spaced apart from the semiconductor stack structure.


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