Memory architecture for serial eeproms

Abstract

In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.