The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2024
Filed:
Apr. 22, 2022
Seagate Technology Llc, Fremont, CA (US);
Jon D. Trantham, Chanhassen, MN (US);
Praveen Viraraghavan, Chicago, IL (US);
John W. Dykes, Eden Prairie, MN (US);
Ian J. Gilbert, Chanhassen, MN (US);
Sangita Shreedharan Kalarickal, Eden Prairie, MN (US);
Matthew J. Totin, Excelsior, MN (US);
Mohamad El-Batal, Superior, CO (US);
Darshana H. Mehta, Shakopee, MN (US);
SEAGATE TECHNOLOGY LLC, Fremont, CA (US);
Abstract
A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.