The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2024

Filed:

Dec. 01, 2020
Applicant:

Anaflash Inc., San Jose, CA (US);

Inventor:

Seung-Hwan Song, Palo Alto, CA (US);

Assignee:

Anaflash Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06F 7/544 (2006.01); G06N 3/04 (2023.01); G11C 11/22 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/5443 (2013.01); G06N 3/04 (2013.01); G11C 11/54 (2013.01); G06F 2207/4824 (2013.01); G11C 11/2293 (2013.01);
Abstract

A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.


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