The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Jun. 24, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Srinivasa Chakravarthy, Bangalore, IN;

Prasanth Viswanathan Pillai, Bangalore, IN;

Mohammed Arif, Bangalore, IN;

Bhargov Bora, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); G06F 1/06 (2006.01); G06F 11/263 (2006.01); H03K 21/02 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); G06F 1/06 (2013.01); G06F 11/263 (2013.01); H03K 21/02 (2013.01);
Abstract

An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.


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