The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Nov. 03, 2023
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

HongJu Lee, Paju-si, KR;

Hyunwoo Kim, Paju-si, KR;

Beom-Jin Kim, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3275 (2016.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 3/211 (2013.01); G09G 3/3275 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0252 (2013.01); G09G 2330/021 (2013.01); H03F 2200/366 (2013.01); H03F 2200/87 (2013.01);
Abstract

Disclosed is an amplifier circuit comprising a first stage having first and second input terminals, a second stage configured to amplify a voltage supplied from the first stage and including a pull-up node and a pull-down node, a third stage including an output terminal, a tenth PMOS transistor, and a tenth NMOS transistors having gate electrodes respectively connected to the pull-up node and the pull-down node of the second stage, the third stage configured to perform a pull-up driving and pull-down driving of the amplified voltage, a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node and the first boosting circuit configured to increase a current in the first stage, and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node and configured to increase the current in the first stage.


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