The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Aug. 25, 2017
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Naoki Komai, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H04N 25/79 (2023.01); H04N 25/11 (2023.01);
U.S. Cl.
CPC ...
H01L 27/14645 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/1464 (2013.01); H01L 27/14683 (2013.01); H01L 27/1469 (2013.01); H04N 25/79 (2023.01); H01L 27/14623 (2013.01); H04N 25/11 (2023.01);
Abstract

The present disclosure relates to a solid state imaging device capable of further decreasing a chip size, a solid state imaging device manufacturing method, and an electronic apparatus. A solid state imaging device includes: a semiconductor substrate with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with wiring connected to the plurality of pixels; and a support substrate that is bonded to the wiring layer. A plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer, and through-holes are provided at positions corresponding to the plurality of electrode pads in the support substrate. The present technology can be applied to, for example, a back side irradiation type CMOS image sensor of a wafer level CSP.


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