The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Oct. 22, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-Il Bae, Incheon, KR;

Kang-Ill Seo, Chungcheongbuk-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/3105 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/31053 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/42364 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/6681 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.


Find Patent Forward Citations

Bae, Dong-Il. (2024). Semiconductor device having fin-type field effect transistor and method of manufacturing the same (U.S. Patent No. 12119351). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12119351

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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