The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2024

Filed:

Apr. 15, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Takayuki Ikeda, Kanagawa, JP;

Roh Yamamoto, Toyama, JP;

Shuichi Katsui, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/60 (2006.01); G06F 7/57 (2006.01); G06N 3/08 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G06F 7/60 (2013.01); G06F 7/57 (2013.01); G06N 3/08 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H10B 12/00 (2023.02);
Abstract

A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.


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