The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Sep. 28, 2022
Applicant:

Suzhou Metabrain Intelligent Technology Co., Ltd., Jiangsu, CN;

Inventors:

Kang Su, Jiangsu, CN;

Fen Guo, Jiangsu, CN;

Hongtao Man, Jiangsu, CN;

Tuo Li, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); G06F 7/501 (2006.01); H03K 19/02 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 19/02 (2013.01); G06F 7/501 (2013.01); H03K 19/21 (2013.01);
Abstract

An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.


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