The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Dec. 07, 2022
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Edward Lee, Fullerton, CA (US);

Michael Chapman, Long Beach, CA (US);

Ravi Ananth, Laguna Niguel, CA (US);

Michael A de Rooij, Playa Vista, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A circuit to enhance the driving capability of conventional inverting bootstrapping GaN drivers. When the inverting driver input is logic high and the driver output is off, the voltage stored on the first bootstrap capacitor for turning on the high side (pull-up) FET of the inverting driver is charged to the full supply voltage using an active charging FET, instead of using a diode or diode-connected FET in a conventional bootstrapping driver. The gate voltage of the active charging FET is bootstrapped to a voltage higher than supply voltage by a second bootstrap capacitor that connects to the inverting driver input, which is at a logic high. The second bootstrap capacitor is charged by an additional diode or diode-connected FET connected to the supply voltage when the inverting driver input is a logic low.


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