The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2024

Filed:

Jul. 14, 2023
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Hsien-Wen Wan, Kaohsiung, TW;

Yi-Ting Cheng, Kaohsiung, TW;

Ming-Hwei Hong, Hsinchu County, TW;

Juei-Nai Kwo, Hsinchu, TW;

Bo-Yu Yang, New Taipei, TW;

Yu-Jie Hong, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28255 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.


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