The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Apr. 08, 2023
Applicant:
R&d 3 Llc, Round Rock, TX (US);
Inventor:
Ravindraraj Ramaraju, Round Rock, TX (US);
Assignee:
R&D 3 LLC, Round Rock, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/14 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/18 (2006.01); G11C 11/404 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/56 (2006.01); G11C 16/30 (2006.01); G11C 8/16 (2006.01); G11C 11/405 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 5/063 (2013.01); G11C 7/065 (2013.01); G11C 7/08 (2013.01); G11C 7/14 (2013.01); G11C 7/18 (2013.01); G11C 11/404 (2013.01); G11C 11/4045 (2013.01); G11C 11/4091 (2013.01); G11C 11/565 (2013.01); G11C 16/30 (2013.01); G11C 8/16 (2013.01); G11C 11/405 (2013.01); G11C 11/4094 (2013.01); G11C 2207/2254 (2013.01);
Abstract
The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.