The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Oct. 27, 2023
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Geoffrey Charles Gardner, West Lafayette, IN (US);

Sergei Vyatcheslavovich Gronin, West Lafayette, IN (US);

Flavio Griggio, Seattle, WA (US);

Raymond Leonard Kallaher, West Lafayette, IN (US);

Noah Seth Clay, West Lafayette, IN (US);

Michael James Manfra, West Lafayette, IN (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10N 60/10 (2023.01); H10N 60/01 (2023.01);
U.S. Cl.
CPC ...
H10N 60/0184 (2023.02); H10N 60/128 (2023.02);
Abstract

Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount. The method further includes forming a superconducting layer over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.


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