The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2024
Filed:
Sep. 20, 2021
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/66666 (2013.01); H01L 29/6684 (2013.01); H01L 29/7827 (2013.01); H01L 29/78391 (2014.09); H01L 21/02252 (2013.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 21/02636 (2013.01); H01L 21/31116 (2013.01);
Abstract
Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.