The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Oct. 26, 2022
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Nirmal Shende, Santa Clara, CA (US);

Nedeljko Varnica, San Jose, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G06N 3/04 (2023.01); G06F 11/10 (2006.01); G06N 3/02 (2006.01); G06N 20/00 (2019.01); H03M 13/29 (2006.01); H03M 13/37 (2006.01); H03M 13/39 (2006.01); H03M 13/45 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1108 (2013.01); G06N 3/04 (2013.01); H03M 13/1125 (2013.01); G06F 11/1068 (2013.01); G06N 3/02 (2013.01); G06N 20/00 (2019.01); H03M 13/1105 (2013.01); H03M 13/2948 (2013.01); H03M 13/3707 (2013.01); H03M 13/3746 (2013.01); H03M 13/3927 (2013.01); H03M 13/458 (2013.01); H04L 1/005 (2013.01);
Abstract

A method of reading data read from a NAND Flash memory device includes decoding a set of data read from the device, using an initial set of hard bit thresholds, when the decoding is unsuccessful, performing a read-retry operation that retries the decoding using, in order, each of a plurality of entries in a read-retry table of hard bit thresholds, stopping when decoding based on one of the entries is successful, and when the read-retry operation is unsuccessful, performing a deep retry operation using a set of log-likelihood ratios (LLRs) that vary in at least one of values or symmetries. NAND Flash memory apparatus includes a Flash media controller, a data bus, and an adaptive LLR engine configured to generate, for use in a deep retry operation, a set of LLRs that, and to transfer the set of LLRs that vary to the media controller via the bus.


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