The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Oct. 24, 2022
Applicant:

Analog Devices International Unlimited Company, Limerick, IE;

Inventors:

Sharvil Pradeep Patil, Toronto, CA;

Asha Ganesan, Markham, CA;

Hajime Shibata, Toronto, CA;

Donald W. Paterson, Winchester, MA (US);

Haiyang Zhu, Winchester, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0604 (2013.01); H03M 1/1038 (2013.01); H03M 1/1047 (2013.01); H03M 1/164 (2013.01);
Abstract

Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a 'feedforward' path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.


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