The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2024
Filed:
Dec. 06, 2021
Infineon Technologies Ag, Neubiberg, DE;
Raphael Hellwig, Regensburg, DE;
Philip Amos, Berkshire, GB;
Walter Hartner, Bad Abbach-Peissing, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A circuit arrangement has a chip arrangement in the form of an embedded Wafer Level Ball Grid Array (eWLB) arrangement with solder contacts on one side and a thermal interface on a side of the chip arrangement facing away from the solder contacts which is designed to dissipate heat from the semiconductor chip. In examples, the thermal interface has a thermally and electrically conductive material, wherein in a top view of the chip arrangement, a contact area in which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the fan-out area. In examples, the thermal interface has at least one RF absorption layer which is designed to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.