The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Feb. 18, 2022
Applicant:

Daewon Semiconductor Packaging Industrial Company, Santa Clara, CA (US);

Inventors:

Sunna Chung, Seoul, KR;

Ryan Park, Santa Clara, CA (US);

Jin Chae, Santa Clara, CA (US);

Matthew Stanton Whitlock, Santa Clara, CA (US);

Jonathan Kevin Lie, Santa Clara, CA (US);

Athens Okoren, Hanam, KR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B65D 85/48 (2006.01); H01L 21/673 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67383 (2013.01); H01L 21/67346 (2013.01); H01L 21/67366 (2013.01); H01L 21/67373 (2013.01); H01L 21/67326 (2013.01);
Abstract

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.


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