The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2024

Filed:

Jan. 13, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Christopher L. Mills, Saratoga, CA (US);

Sung Hee Park, Cupertino, CA (US);

Assignee:

APPLE INC., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/24 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/24 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01);
Abstract

Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.


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