Flash memory scheme capable of controlling flash memory device automatically generating debug information and transmitting debug information back to flash memory controller without making memory cell array generating errors

Abstract

A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.