Digital pdm microphone interface

Abstract

A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising ('Right') or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption. In a dual PDM microphone system, it is desirable to operate in a low power mode with a single microphone at times and to operate with the full functionality (and power consumption) of both microphones at other times. In a conventional system, both PDM microphones share both the PDMDAT and PDMCLK signal lines. Thus both microphones must be clocked even if only one is being used. This wastes power in both the PDMCLK output buffer (driving both loads even if one is not being used) as well as in the unused microphone (where all of the clock circuits are active and switching). A novel PDM microphone interface is disclosed that provides a three signal interface comprising a separate PDMCLK signal to each microphone while maintaining a single common PDMDAT line.