The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Aug. 12, 2021
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Md. Nazmus Sakib, Seattle, WA (US);

Ronald Aigner, Redmond, WA (US);

Ling Tony Chen, Bellevue, WA (US);

Peter David Waxman, Seattle, WA (US);

David Guy Weston, Seattle, WA (US);

Bryan David Kelly, Carnation, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); G06F 9/455 (2018.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3234 (2013.01); G06F 9/45558 (2013.01); H04L 9/083 (2013.01); G06F 2009/45587 (2013.01);
Abstract

Methods, systems, apparatuses, and computer-readable storage mediums described herein enable executable code of a hardware security platform (HSP) circuit to communicate with a hypervisor in a separate processor. The hypervisor generates and manages virtual machines. The HSP code comprises trusted platform module (TPM) logic, that processes TPM commands received via the hypervisor, and in response to the processing, communicates security information (e.g., measurements, keys, authorization data) with the virtual machines via the hypervisor. The TPM logic receives security information related to a virtual machine from the hypervisor and stores the security information in non-volatile memory of the HSP circuit, where security information from a particular VM is distinguishable from security information from another VM in the HSP memory. The hypervisor (and VMs) communicate via a network fabric with the HSP circuit within an SOC, or the HSP may reside on a discrete chip and communicate via a secure encrypted channel.


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