The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Oct. 19, 2021
Applicant:

Depuy Synthes Products, Inc., Raynham, MA (US);

Inventor:

Laurent Blanquart, Westlake Village, CA (US);

Assignee:

DePuy Synthes Products, Inc., Raynham, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); A61B 1/00 (2006.01); A61B 1/05 (2006.01); A61B 1/06 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 27/12 (2006.01); H04N 23/56 (2023.01); H04N 25/75 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01); H01L 31/028 (2006.01); H01L 31/0296 (2006.01); H01L 31/0304 (2006.01); H04N 23/50 (2023.01);
U.S. Cl.
CPC ...
H01L 27/14603 (2013.01); A61B 1/00009 (2013.01); A61B 1/051 (2013.01); A61B 1/0676 (2013.01); H01L 24/17 (2013.01); H01L 24/20 (2013.01); H01L 24/28 (2013.01); H01L 25/0657 (2013.01); H01L 27/124 (2013.01); H01L 27/146 (2013.01); H01L 27/14601 (2013.01); H01L 27/14609 (2013.01); H01L 27/14618 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14638 (2013.01); H01L 27/1464 (2013.01); H01L 27/14641 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 27/1469 (2013.01); H04N 23/56 (2023.01); H04N 25/75 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01); H01L 31/028 (2013.01); H01L 31/0296 (2013.01); H01L 31/0304 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/381 (2013.01); H04N 23/555 (2023.01);
Abstract

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.


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