The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Aug. 29, 2022
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Chunping Long, Beijing, CN;

Yong Qiao, Beijing, CN;

Xinyin Wu, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/12 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0292 (2013.01); H01L 27/027 (2013.01); H01L 27/1251 (2013.01); H01L 27/1259 (2013.01); H01L 27/127 (2013.01); H01L 27/0266 (2013.01); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); H02H 9/045 (2013.01);
Abstract

Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.


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