The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

May. 02, 2023
Applicant:

Psiquantum, Corp., Palo Alto, CA (US);

Inventors:

Ramakanth Alapati, Dublin, CA (US);

Gabriel J. Mendoza, San Francisco, CA (US);

Assignee:

PSIQUANTUM, CORP., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0232 (2014.01); G02B 6/36 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); G02B 6/3636 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/4882 (2013.01); H01L 23/3672 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 24/85 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/48157 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1903 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19107 (2013.01);
Abstract

Techniques disclosed herein relate generally to integrating photonic integrated circuits and electronic integrated circuits in a same package. A device includes a semiconductor substrate and a die stack on the semiconductor substrate. The die stack includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. The PIC die includes a PIC substrate and a photonic integrated circuit formed on the PIC substrate. The EIC die includes an EIC substrate and an electronic integrated circuit formed on the EIC substrate. The EIC die and the PIC die are bonded such that the PIC substrate and the EIC substrate are disposed on opposing sides of the die stack. The PIC substrate is bonded to the semiconductor substrate. The device also includes a cooling plate bonded to the EIC substrate.


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