The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jun. 06, 2022
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Andre Gunther, San Jose, CA (US);

Jeffrey Alan Goswick, San Jose, CA (US);

Rob Cosaro, San Jose, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3212 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3212 (2013.01); G06F 1/3296 (2013.01);
Abstract

Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.


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