The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Sep. 20, 2019
Applicant:
Sunrise Memory Corporation, Fremont, CA (US);
Inventors:
Raul Adrian Cernea, Santa Clara, CA (US);
Wu-Yi Henry Chien, San Jose, CA (US);
Eli Harari, Saratoga, CA (US);
Assignee:
SUNRISE MEMORY CORPORATION, San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/20 (2023.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 43/30 (2023.01);
U.S. Cl.
CPC ...
H10B 43/20 (2023.02); H01L 21/28525 (2013.01); H01L 21/30604 (2013.01); H01L 21/32133 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53271 (2013.01); H10B 43/30 (2023.02);
Abstract
Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.