The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Jun. 01, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kevin Bowles, Mission Viejo, CA (US);

Chirag Maheshwari, San Diego, CA (US);

Divya Gangadharan, San Diego, CA (US);

Venkat Narayanan, San Diego, CA (US);

Masoud Zamani, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H03K 19/003 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1774 (2013.01); H03K 19/00323 (2013.01); H03K 19/17744 (2013.01); H03K 19/20 (2013.01);
Abstract

In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.


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