The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Jul. 25, 2022
Applicant:

Denso Corporation, Kariya, JP;

Inventor:

Yuuki Suzuki, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/00 (2006.01); H01G 4/38 (2006.01); H02M 1/15 (2006.01); H02M 1/44 (2007.01); H02M 7/48 (2007.01);
U.S. Cl.
CPC ...
H02M 1/15 (2013.01); H01G 4/38 (2013.01); H02M 1/44 (2013.01); H02M 7/003 (2013.01); H02M 7/48 (2013.01);
Abstract

A capacitor module includes a smoothing capacitor, a P-side Y capacitor and a N-side Y capacitor as noise absorbing capacitors, a capacitor case, a P-side bus bar, a N-side bus bar, and a ground bus bar. A virtual plane along a P-side electrode surface, which is an electrode surface on a high potential side of the smoothing capacitor, is referred to as a P-side virtual plane. A virtual plane along a N-side electrode surface, which is an electrode surface on a low potential side of the smoothing capacitor, is referred to as a N-side virtual plane. A region between the P-side virtual plane and the N-side virtual plane is defined as a PN region. The entire noise absorbing capacitor and the entire ground bus bar are arranged in the PN region.


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