The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Dec. 20, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Buddhika Abesingha, Escondido, CA (US);

Arezu Bagheri, San Diego, CA (US);

Gregory Szczeszynski, Hollis, NH (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 1/088 (2006.01);
U.S. Cl.
CPC ...
H02M 1/088 (2013.01); H02M 1/0006 (2021.05); H02M 1/0009 (2021.05); H02M 1/0032 (2021.05); H02M 3/158 (2013.01);
Abstract

A switching power converter architecture that is efficient across its entire power range, regardless of load level, by partitioning the power devices into segments for optimal gate drive and providing a local variable-voltage driver for each power device segment. Power device segments may be selectively enabled or disabled based on the level of power to be delivered to a load. In addition, an adaptive gate drive scheme enables dynamic control of the Rand Qvalues for each power converter device so that the power devices may operate at the lowest Rvalue at or near maximum power levels for reduced conduction losses, at the lowest R×Qproduct value at mid-level loads for peak efficiency, and at the lowest Qvalue at light loads for reduced switching losses.


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