The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
May. 11, 2021
Applicant:
Infineon Technologies Austria Ag, Villach, AT;
Inventors:
Oliver Haeberlen, Villach, AT;
Walter Rieger, Arnoldstein, AT;
Assignee:
Infineon Technologies Austria AG, Villach, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 27/06 (2006.01); H01L 27/085 (2006.01); H01L 29/20 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/43 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 27/0605 (2013.01); H01L 27/085 (2013.01); H01L 29/2003 (2013.01); H01L 29/201 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/1066 (2013.01); H01L 29/41766 (2013.01); H01L 29/432 (2013.01);
Abstract
A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.