The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Nov. 22, 2021
Applicant:

Korea University Research and Business Foundation, Seoul, KR;

Inventors:

In-Hwan Lee, Seoul, KR;

Taehwan Kim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 27/15 (2006.01); H01L 33/06 (2010.01); H01L 33/24 (2010.01); H01L 33/32 (2010.01); H01L 33/38 (2010.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 27/156 (2013.01); H01L 33/0075 (2013.01); H01L 33/0093 (2020.05); H01L 33/06 (2013.01); H01L 33/24 (2013.01); H01L 33/32 (2013.01); H01L 33/387 (2013.01); H01L 33/44 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01);
Abstract

Disclosed is a technology of preferentially forming an ohmic contact layer and a conductor layer before separating a nanorod light emitting diode (LED) from a substrate, thereby being capable of omitting a heat treatment process performed at high temperature after aligning the nanorod LED, and, accordingly, preventing electrical short while maximizing the quantum efficiency of the nanorod LED and increasing a selection range of a material constituting a light emitting diode (LED) display. More particularly, the nanorod LED includes a first semiconductor layer; a multi-quantum well structure layer; a second semiconductor layer; and a conductor layer formed on at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer, wherein a length and shape of the conductor layer are controlled such that the multi-quantum well structure layer is disposed between two electrodes of the electrode pattern on which the conductor layer is to be aligned.


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