The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Sep. 23, 2022
Applicant:

Apogee Semiconductor, Inc., Plano, TX (US);

Inventors:

Emily Ann Donnelly, Whitesboro, TX (US);

Mark Hamlyn, Murphy, TX (US);

Kyle Schulmeyer, Salida, CO (US);

Gregory A. Magel, Dallas, TX (US);

Assignee:

Apogee Semiconductor, Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); G01T 1/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); G01T 1/026 (2013.01); H01L 21/823425 (2013.01); H01L 27/088 (2013.01);
Abstract

Devices with increased susceptibility to ionizing radiation feature multiple parasitic transistors having leakage currents that increase with total ionizing dose (TID) due to negative threshold shifts from radiation-induced charge buildup in the field oxide. Leakage currents of parasitic edge transistors associated with active region sidewalls under a gate are enhanced using branching gate patterns that increase the number of these sidewalls. Other variations combine parasitic edge transistors with parasitic field transistors formed under the field oxide between active regions, or between n-wells and active regions. Arrays of such devices connected in parallel further multiply leakage currents, while novel compact designs increase the density and hence the sensitivity to TID for a given circuit area. These NMOS-based radiation-intolerant devices can be integrated with more radiation-tolerant CMOS integrated circuits using commercial processes, to produce circuits having a level of radiation intolerance required for export, or to be used as dosimeters.


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