The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Jun. 03, 2023
Applicant:
Zeno Semiconductor, Inc., Sunnyvale, CA (US);
Inventors:
Jin-Woo Han, San Jose, CA (US);
Neal Berger, Cupertino, CA (US);
Yuniarto Widjaja, Cupertino, CA (US);
Assignee:
Zeno Semiconductor, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/401 (2006.01); G11C 5/06 (2006.01); G11C 8/00 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 29/50 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/401 (2013.01); G11C 11/4076 (2013.01); G11C 29/50 (2013.01); H10B 12/20 (2023.02); G11C 5/06 (2013.01); G11C 8/00 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 16/0416 (2013.01); G11C 16/08 (2013.01); G11C 2211/4016 (2013.01);
Abstract
A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.