The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Jun. 01, 2023
Applicants:

Wuhan Tianma Micro-electronics Co., Ltd., Wuhan, CN;

Wuhan Tianma Micro-electronics Co., Ltd. Shanghai Branch, Shanghai, CN;

Inventors:

Zhiyong Xiong, Shanghai, CN;

Yaolin Wang, Shanghai, CN;

Rui Ding, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09F 9/30 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09F 9/301 (2013.01); G09G 2300/0426 (2013.01); G09G 2330/028 (2013.01); H01L 27/1218 (2013.01); H01L 27/124 (2013.01);
Abstract

A display panel has a display region and a frame region outside the display region. The display region includes a plurality of pixel circuits. The display panel includes a base substrate, a buffer layer, a semiconductor layer, a power signal layer, and an auxiliary circuit layer. The buffer layer is on a side of the base substrate. The buffer layer includes an a-Si layer. The semiconductor layer is on a side of the buffer layer away from the base substrate. The power signal layer is on a side of the semiconductor layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit.


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