The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Sep. 25, 2020
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Benjamin Tsien, Santa Clara, CA (US);

Alexander J. Branover, Boxborough, MA (US);

John Petry, Santa Clara, CA (US);

Chen-Ping Yang, Santa Clara, CA (US);

Rostyslav Kyrychynskyi, Markham, CA;

Vydhyanathan Kalyanasundharam, Santa Clara, CA (US);

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI Technologies ULC, Markham, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 1/30 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/4401 (2018.01); G06F 9/46 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3005 (2013.01); G06F 9/3877 (2013.01); G06F 9/4418 (2013.01); G06F 9/463 (2013.01); G06F 13/4022 (2013.01);
Abstract

A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.


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