The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

May. 08, 2023
Applicant:

Celera, Inc., San Jose, CA (US);

Inventors:

Calum MacRae, Charlotte, NC (US);

John Mason, Sunnyvale, CA (US);

Karen Mason, Sunnyvale, CA (US);

Assignee:

Celera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/373 (2020.01); G06F 2111/12 (2020.01);
Abstract

In some embodiments, a computer-implemented method of generating a resistor comprises receiving a first resistor value, converting the resistor value into a plurality of resistor layout segments, and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value.


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