The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Mar. 09, 2023
Applicant:

Dell Products L.p., Hopkinton, MA (US);

Inventors:

Ashok Tamilarasan, Shrewsbury, MA (US);

Vamsi K Vankamamidi, Hopkinton, MA (US);

Amitai Alkalay, Kadima, IL;

Assignee:

Dell Products L.P., Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 2212/1024 (2013.01);
Abstract

Caching techniques can include: receiving a read I/O operation requesting to read from a logical address; determining whether a mapping cache includes a descriptor for the logical address, the mapping cache including two hash tables; responsive to determining that the mapping cache includes the descriptor for the logical address, performing read hit mapping cache processing which includes using a physical location identified by the descriptor to read content stored at the logical address; and responsive to determining that the mapping cache does not include the descriptor for the logical address, performing read miss mapping cache processing which includes adding the descriptor to the mapping cache. Read miss mapping cache processing can include adding the descriptor to a first hash table, used to access the descriptor by the logical address, and adding the descriptor to a second hash table used to access the descriptor by the physical location.


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