The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Dec. 15, 2022
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Aravind Bhaskara, San Diego, CA (US);
Zhurang Zhao, San Diego, CA (US);
Kiran Bhagwat, San Diego, CA (US);
Michael Tipton, Midlothian, VA (US);
Joshua Stubbs, Longmont, CO (US);
Jyotirmoy Das, San Diego, CA (US);
Thomas Tang, Pleasanton, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/08 (2006.01); G06F 1/26 (2006.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/08 (2013.01); G06F 1/3203 (2013.01);
Abstract
Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.